Orinoco assumes a macro based design approach: in this approach the
behavioral specification is mapped onto a netlist of register transfer
level (RTL) blocks (hard-/soft-macros like Synopsys DesignWare
components, memories and IP blocks).
Reflecting this design style Orinoco estimates the power consumption of
specific architectures by applying power macro models of the RT blocks
involved: Data path components like computational units, registers and
multiplexers are estimated using an enhanced Hamming distance model
based on interpolation and regression. Embedded memories are handled
using nonlinear regression based black box modelling. Reference data for
the model building is obtained by a characterization procedure using
gate-level simulation. This takes several CPU hours, but only has to be
performed once per technology. Off-chip memories and pads are
represented by data sheet models. The clock power estimation uses the
accumulated input capacitances of all registers, whereas the clock tree
wiring and buffers are currently neglected. Clock power is therefore
strongly dependent on the number of registers allocated. The newest
version also estimates controller power and takes into account power for
interconnect.
PRODUCTS