CHARTER Projects
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Our Projects
Current Projects: InTraLED - INdustry-driven TRAining for Low-power European Designers Motivation The target of the InTraLed project is the developement and the realization of 'Methods and Tools for Low-Power Design' courses. The InTraLed consortium consists of seven partners. In addition to OFFIS and OSC, there are two academic partners (Polito, University of Patras), and three industrial ones (STMicroelectronics, Intracom, BullDAST, OSC). more ... POET - Power Optimization of Embedded Systems The main objective of the POET project is to develop a new design methodology and tool suite (ORINOCO) for power estimation and optimisation in heterogeneous embedded SoC designs. The key innovation of the approach is to enable design space exploration for low power system architectures, algorithm optimisations and system partitioning - from the earliest design steps seamlessly through to RT level (i.e. to the interface with standard industrial synthesis tools). The POET design framework will operate at each level of abstraction, i.e. algorithmic, hardware/software partition, cycle-accurate RT level. POET tools will manage and optimise all major contributors to power dissipation in large SoC designs such as ASICs, cores and processors, memories, communication and I/O interfaces. more ... MARLOW - A central market place for dissemination of lowpower micro-electronics design knowledge The ability of designing low-power circuits and applications is key for electronics industries aiming at market competitiveness in the "wireless era". Building upon the results of the TARDIS ESD-LPD Cluster, the MARLOW project will offer a coordinated take-up action to disseminate to a broad audience low-power electronic design knowledge, by providing access means to training, expertise and background information. The MARLOW project will create a flexible and dynamic framework that will favor the exchange of information and the transfer of technology among the partners and with industry and SMEs. Services that will be provided include, but are not limited to a comprehensive low-power design WEB-portal, a technology and methodology roadmap giving directions for future challenging areas of research and development, on-demand consulting and points of technical synchronization for the low-power design community. The MARLOW project started on the first of September 2002. It is expected that at the beginning of the year 2003 the WEB-portal has been constructed and more contents will become available. more ... LP-System - Power estimation of integrated circuits based on system specifications in C/C++ language The OFFIS research institute establishes a low power design flow for embedded systems as one main objective. Within previous an ongoing projects a methodology for estimating power of integrated circuits and the base technology of an EDA tools called ORINOCO have been developed. Input for this tool is a behavioral description of hardware in the language VHDL. At system level specifications of multimedia and communication systems typically are described in C/C++. For this reason within this project a C/C++ based low power system design process shall be supported. Manual instrumentation of specifications of complex systems for extracting activity information is not to be expected by a designer, because of the amount of instructions that have to be inserted into the code. Only automatic processing of C/C++ source code leads to the user's acceptance of a design tool in this field. LP System will extend ORINOCO to enable power estimation and optimization of C/C++ algorithms to be implemented in hardware. more ... PRO-DASP - Power Reduction for Digital Audio Processing The aim of this project is the design of low power optimized systems for digital signal processing of acoustic signals. For these applications a design methodology will be developed and formalized across all levels of abstraction, reflecting the interactions between algorithm and architecure at this point of system- and hardware-design. more ... Completed Projects: HIMOK - Highest possible integration of mobile communication technology The objective of the HIMOK project is to extend the Bosch design flow to allow prediction of power being dissipated. Starting from a hardware description in the language C power consumption has to be estimated as described above. more ... PEOPLE - Power Estimation of Embedded Systems The objective of the PEOPLE project is the development of a tool-suite of power estimators for embedded systems which enables a design flow for fast, yet accurate power estimation and optimization of designs starting at the behavioural level of abstraction downto the register transfer level. The target architecture of the systems to be designed using this design flow may contain hard and soft macros, RAMs, ROMs, and complex IP cores like processors. The tool-suite consists of power estimators for the software part, the behavioural level and RT-level as well as for memories. more ... VIP - Versatile Integrated Payphone Objectives are to conceive and demonstrate the realisation of a payphone with upgraded services thinking on internet access, e-mail, banking, voice messaging, disabled access, etc. The latter advantage will allow payphones to be ready for the next century, giving the possibility to people to access modern multimedia and web services via such a public device. more ... EURIPIDES - Methods to optimize and characterise the power dissipation of reusable modules One main feature of the power dissipation of a circuit is its dependence on the operation status and input data of the circuit. In the scope of this partial project OFFIS is going to elaborate a power dissipation model for such components that enables a data dependent estimation of power dissipation of modules. These models then can be applied in the range of optimization tools and analysis systems of the project partners in order to minimize and charcterise the power consumption of reusable components and in the area of analysis of system structures corresponding to characterized circuits. more ... POSEIDON - Power Optimization and Simulation: Efficient strategies in deep sub micron CMOS more ... JESSI - The Project Design for Low-Power Consumption As part of the JESSI (Joint European Submicron Silicon Program) AC-8 application project Synthesis, Optimization and Analysis OFFIS has been working together with Philips Research in Eindhoven (Netherlands) on low power design tools for integrated CMOS circuits. Philips focussed on optimization tools and OFFIS provided the power analysis tools, which are needed to evaluate different design alternatives. more ... Further Infromation: OFFIS Research Institute - Projects University of Oldenburg - Projects |
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