LowPower Competence Group

Collection of own papers

E. Schmidt, G. von Cölln, L. Kruse, F. J. Theeuwen, W. Nebel:
Memory Power Models for Multi-Level Power Estimation and Optimization
accepted at IEEE Transactions on VLSI Systems,
Special Issue on Low Power Electronics and Design, 2001

Domenik Helms, Eike Schmidt, Arne Schulz, Ansgar Stammermann, Wolfgang Nebel:
An Improved Power Macro-Model for Arithmetic Datapath Components
Proceedings of PATMOS02, Seville, Spain, Sept. 2002, o.O.: Springer

Allara, A.; Bombana, M.; Kruse, L.; Nebel, W.; Schmidt, E.; Stammermann, A.:
VHDL Behavioural Power Estimation for Telecom Devices.
accepted for FDL 2001, Lyon, France, September 3-7, 2001.

Schmidt, E.; Schulz, A.; Kruse, L.; Nebel W.:
Automatic Generation of Complexity Functions for High-Level Power Analysis.
accepted for PATMOS 2001, Yverdon-Les-Bains, Switzerland, September 26-28, 2001.

Stammermann, A.; Kruse, L.; Nebel, W.; Pratsch, A.; Schmidt, E.; Schulte, M.; Schulz, A.
System Level Optimization and Design Space Exploration for Low Power
accepted for ISSS 2001

Kruse, L.; Schmidt, E.; Jochens, G.; Stammermann, A.; Schulte, M.; Macii, E.; Nebel, W.:
Estimation of Lower and Upper Bounds on the Power Consumption from Scheduled Data Flow Graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9(1),
pp. 3 - 14, February 2001.

W. Nebel und J. Mermet, editors.
Low Power Design of Deep Submicron Electronics.
Kluwer Academic Press, 1997.

Kruse, L.; Schmidt, E.; Jochens, G.; Stammermann, A.; Nebel, W.
Lower Bound Estimation for Low-Power High-Level Synthesis
13th International Symposium on System Synthesis (ISSS 2000), Invited Paper,
Madrid, Spain, 2000. Paris, Frankreich, 2000

This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. The estimated bound takes into account the effects of resource sharing. It is shown that by introducing Lagrangian multipliers and relaxing the low power binding problem to the Assignment Problem, which can be solved in , a tight and fast computable bound is achievable. Experimental results show the good quality of the bound. In most cases, deviations smaller than 5% from the optimal binding were observed. The proposed technique can for example be applied in branch and bound high-level synthesis algorithms for efficient pruning of the design space. The estimated lower bound can also be used as a starting point for low power binding heuristics to find optimal or near optimal binding solutions.

Kruse, L.; Schmidt, E.; Jochens, G.; Stammermann, A.; Nebel, W.
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints
Design and Test Conference in Europe (DATE'00), p. 737,
Paris, France, 2000

Jochens, G.; Kruse, L.; Schmidt, E.; Stammermann, A.; Nebel, W.
Power Macro-Modelling for Firm-Macros
PATMOS'00,
Goettingen, Germany, 2000

An approach for power modelling of parameterized, technology independent design components (firm-macros) is presented. Executable simulation models in form of C++ classes are generated by a systematic procedure that is based on statistical modelling and table look-up techniques. In contrast to other table look-up based approaches the proposed model separately handles the inputs of a component, and with this it allows to model the effects of corresponding joint-dependencies. In addition, a technique for the generation of executable models is presented. The generated models are optimized with respect to simulation performance and can be applied for power analysis and optimization tasks on the behavioral and architectural level. Results are presented for a number of test cases which show the good quality of the model.

Kruse, L.; Schmidt, E.; Jochens, G.; Nebel, W.
Lower Bounds on the Switching Activity in Scheduled Data Flow Graphs with Resource Constraints
Technical Report University of California at Irvine,
ICS-99-33, 1999

Kruse, L.; Schmidt, E.; Jochens, G.; Nebel, W.
Low Power Binding Heuristics
PATMOS'99, pp. 41 - 50,
Kos, Greece, 1999

This paper addresses the problem of solving the low power binding problem under resource constraints, i.e. binding operations and variables to resources such that power consumption of these resources is minimized. Three heuristics with different performance and quality of the produced bindings are presented. The best heuristic delivered the best possible binding in 55 out of 74 test cases while the other binding costs were within 5% of the optimum.

Kruse, L.; Schmidt, E.; Jochens, G.; Nebel, W.
Lower and Upper Bounds on the Switching Activity in Scheduled Data Flow Graphs
International Symposium on Low Power Electronics and Design (ISLPED'99), pp. 115 - 120,
San Diego, California, 1999

In this paper we present an approach to calculate lower and upper bounds for the switching activity in scheduled data flow graphs. The technique can be used to prune the design space in high level synthesis for low power before allocation and binding of functional units and registers. The low power allocation and binding problem is formulated. It is shown that this problem can be relaxed to the bipartite weighted matching problem which is solvable in where n is the number of functional units or registers, respectively. The application of the technique on benchmarks shows the tightness of the bounds. Most of the investigated bounds were less than 1% off the minimum respectively maximum solutions.

Jochens, G.; Nebel, W.
Modellierung und Simulation der Verlustleistung in datenflussorientierten Schaltungen (in german)
SSE-Workshop,
Berlin, 12./13.4. 1999

Jochens, G.; Kruse, L.; Schmidt, E.; Nebel, W.
A New Parameterizable Power Macro-Model for Datapath Components
DATE'99, pp. 29 - 36,
Munich, Germany, 1999

We propose a novel power macro-model which is based on the Hamming-distance of two consecutive input vectors and additional information on the module structure. The model is parameterizable in terms of input bit-widths and can be applied to a wide variety of datapath components. The good trade-off between estimation accuracy, model complexity and flexibility makes the model attractive for power analysis and optimization tasks on a high livel of abstraction. Furthermore, a new approach is presented, that allows to calculate the average Hamming-distance distribution of an input data stream. It will be demonstrated, that the application of Hamming-distance distribuitons, instead of only the averae values, improves the estimation accuracy for a number of typical DSP-modules and data streams.

Schmidt, E.; Kruse, L.; Jochens G.; Huijbregts, E.; Seelen, E. A.; Nebel, W.
Power Consumption of On-Chip ROMs: Analysis and Modeling
Proceedings of PATMOS'98, pp. 171 - 180,
Lyngby, Denmark, 1998

This paper addresses the problem of modeling the power consumption of on-chip ROMs for gate-level and RT-level power estimations. A route to memory power model development is presented that is also applicable to other memory architectures. The model proposed operates within an error margin of less than 5%.

Rabe, D.;Jochens, G.;Kruse, L.; Nebel, W.
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs
Design and Test Conference in Europe (DATE'98),
Paris, France, 1998

Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at high performance. The high accuracy is achieved by putting emphasis on delay- and power-modelling. The impact of these modelling factors on accuracy and performance is demonstrated by comparing GliPS to other tools on circuit-level and a simple toggle count based power simulator TPS on gate level.

Kruse, L.; Rabe, D.; Nebel, W.
VHDL Power Simulator: Power Analysis at Gate-Level
CHDL'97, Hardware Description Languages and their Applications, ISBN 0-412-78810-1, pp. 317-333,
Toledo, Spain, 1997

Power consumption of integrated circuits becomes more and more an important issue in the design phase. In this paper a new application of VHDL for gate-level power analysis and accurate timing verification is presented. Our VHDL Power Simulator (VPS) is able to accurately estimate the mean power consumption of a static CMOS standard cell design described in VHDL at gate-level. Additionally VPS increases the timing accuracy of logic level simulation in case of glitches, defined here as pairs of incomplete transitions. This is achieved by modifying the VHDL event handling and propagating ramps instead of infinite slope events. Our tool, implemented as an add-on to Cadence's Leapfrog VHDL simulator, allows to employ a Monte Carlo simulation for mean power consumption analysis while taking rise/fall times and glitches into account. The VHDL descriptions of the cells have to be VITAL Level 1 compliant and only slight modifications of these descriptions have to be done. The library adaptation can be automatically performed. First simulation results show that the accuracy of VPS is within 10% of circuit-level simulation even in case of circuits with high glitch activity.

Jochens, G.; Kruse, L.; Nebel, W.
Application of Toggle-Based Power Estimation to Module Characterization
PATMOS'97,
Leuven a Neuve, Belgium, 1997

This paper discusses the advantages and disadvantages of a fast methodology for power estimation of integrated CMOS circuits at gate level for RT-module power characterization. The methodology is based on a simple toggle count mechanism and embodied in our Toggle Power Simulator (TPS). TPS takes output loads and precharacterized gate internal power losses into account. The tool is integrated into the design kit of Atmel ES2 which itself is an add-on to the Cadence Design Framework II. Speed and accuracy of TPS are compared with HSpice simulations for RT level modules and ISCAS'85 benchmarks designed with a 1 micrometer standard cell library. The influence of several simulation parameters is revealed. Within an example it is demonstrated that errors, which are obtained in lower-level simulation, become visible in RT-level simulation results.

Kruse, L.; Jochens, G.; Rabe, D.; Nebel, W.
VHDL Power Simulator (in german)
ES&S'97, pp. 693-702,
Nürnberg, 1997

Kruse, L.; Rabe, D.; Nebel, W.
VHDL Power Simulator (in german)
SICAN Herbsttagung, Tagungsband pp. 25 - 30,
Hannover, Germany, 1996

Rabe, D.; Fiuczynski, B.; Kruse, L.; Welslau, A.; Nebel, W.
Comparison of Different Gate Level Glitch Models
PATMOS'96, pp. 167 - 176,
Bologna, Italy, 1996

Different approaches for glitch modelling on gate level are reviewed and compared with each other by means of a small benchmark circuit and on the base of general CMOS behaviour, which itself is dealt with. These approaches all focus on more precisely modelling glitching behaviour at gate level, which can be used to enhance power estimation at little additional computational costs.

Rabe, D.; Kruse, L.; Nebel, W.
A New Approach in Gate-Level Glitch Modelling
JESSI AC-8 final workshop as part of: IFIP TC10, WG 10.05 workshop on logic & architecture synthesis, pp. 192 - 199,
Grenoble, France, 1996

An enhanced gate-level glitch model for logic simulation is presented. This new approach can be used to enhance logic simulation accuracy and power estimation at little additional computation costs. The simulation algorithm is compatible with common event driven simulation models for glitch-free cases. Only if a possible glitch is detected the simulation is modified by our model. The model is based on common timing characterization data and a few additional constant values. The features of the model are enhanced scheduling of glitch events and prediction of glitch peak voltages, which are essential for precise power estimation.

Timmermann, B.; Jochens, G.; Rabe, D.; Nebel, W.
Transition Density Estimation for Low Power Mapping
JESSI AC-8 final workshop as part of: IFIP TC10, WG 10.05 workshop on logic & architecture synthesis,
Grenoble, France, Dec. 16-18, 1996

Jochens, G.; Rabe, D.; Timmermann, B.; Nebel, W.
Test-IC for Power Consumption Analysis
PATMOS'96, pp. 35 - 44,
Bolgna, Italy, 1996

Verifying simulation results of power analysis tools by circuit-level simulation is time consuming or even impossible for large digital integrated circuits. As a solution this paper presents a test-IC, that uses on-chip Idd measurement and post-processing techniques for automatic power consumption analysis. Features of the test-IC are longtime measurements over up to n = 2.7*10^11 switching cycles, determination of patterns that lead to maximum values of Idd or to values within a defined range. In addition, the effect of varying Idd or the temperature on the power consumption can easily be measured.

Radetzki, M.; Rabe, D.; Timmermann, B.; Nebel, W.
Generation of Binary Patterns with Given Spatiotemporal Correlations
PATMOS'96, pp. 199 - 208,
Bologna, Italy, 1996

Consideration of signal correlations and the choice of input patterns have a significant impact on the results of power estimation for digital CMOS circuits. The pattern analysis and generation method presented in this paper provides a link between probabilistic and explicit simulation techniques. Analysing sample data yields a set of signal probabilities and spatiotemporal correlations. Vice versa, binary pattern sequences can be generated meeting given statistical properties. Furthermore, the tool may be utilized to reduce the amount of stimuli to be applied in explicit simulation while maintaining the properties which are relevant to power dissipation.

Rabe, D.; Timmermann, B.; Nebel, W.
CMOS Library-Characterization for Power Consumption
PATMOS'94, pp. 94 - 105,
Barcelona, Spain, 1994

There is a strong need for power calculations in CMOS-Standard-Cell-Design to obtain essential information for powerrouting and low power synthesis. Power calculations (or current calculations) need a clear definition of which currents in a design are intended to be measured. This seems to be a simple definition, which, however, has not been properly addressed in most previous publications. The purpose of this paper is to point out which currents are reasonable to calculate and how a standard library can be characterized for power calculations using a refined model compared to [1]. This model avoids electrical level simulation during power analysis, but can be used for different power analysis methods on logic level while delivering results which are close to electrical level simulation. The main goal of this paper is to examine which circuit-level-effects can be taken into account within this model.

Rabe, D.; Timmermann, B.; Nebel, W.
Models for Power Dissipation of ASIC Cells
Russian Workshop '94, pp. 34 - 39,
Moscow, Russia, 1994