CHARTER Introduction
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Introduction into Power Estimation
1. Low power? Famous two words: 'low power'. At least they are in our community. They stand for an aspect of electrical systems: the fact that those systems consume energy. And they symbolize all problems and questions around this fact. In general 'low power' could apply to anything from airplane hydraulics to TV-sets. We are applying the term in a very distinct context, however. So let us be more concrete about what we understand as 'low power': We are concerned with the power dissipation of very large scale integrated ("VLSI") digital circuits. Implicitly these are purely non-mechanical systems or parts of systems. This chapter gives an introduction to all people not familiar with the 'low power' aspect of these systems. 1.1 Terminology 1.1.1 Power, energy, etc. What are we looking at? We talked of 'power dissipation' in the preceding section. Power is defined as work done per time (P = W/t). For electrical applications it can easily be computed as: P = U * I (U voltage, I current drawn). Since all electrical work is turned into heat we speak of power 'dissipation'. The term power is only meaningful when the execution time is known. Otherwise we should use accumulated work, 'energy'. When looking at literature you will often also find other terms: - I_avg 'average current' If the voltage U is known, we can compute: Pavg = U * Iavg - Q 'charge' I = Q/t. Given Voltage and time: P = U * I = U * Q/t - Csw_total 'total switched capacitance'. The sum of all capacitancies loaded/unloaded. Given time t and voltage V we can compute: P = U * I = U * Q/t = U * Csw_total * U/t To summarize: under defined circumstances these measures are interchangeable. 1.1.2. Power and time If we look at power we also have to consider the temporal dimension. Are we only interested in average values, maximum values or the concrete power/time curve? The average power dissipation is important for energy delivery and heat removal. The instantaneous power is of interest for electrical effects. The peak power is often used as 'worst case' scenario, for example for the dimensioning of the power grid. 2. Why 'low power'? There are two sides of power consumption: on one hand energy for electronical systems has to be generated and fed into the circuitry. On the other hand the dissipated power is turned into heat on the chip. This heat produces its very own problems. The energy provision is an important issue in mobile systems where battery lifetimes are critical. Prominent examples are handys, PDAs and such. Non-mobile systems are also becoming an issue now. Already 5% of the US power budget is spent for computers. And of course computer chips are not only found in computers. Standby currents of entertainment electronics for example have recently become a sales argument. The industry has estimated that the number of embedded systems in use is already half the number of people on this planet. But the energy not only has to be generated, it also has to be fed to the consuming circuit in time. The chip-design has to reflect this in the dimension of power grids and decoupling capacities. Furthermore high currents within the chip lead to a decrease in lifetime and limit the reliability. As was mentioned before the dissipated power is turned into heat on the chip surface. As high temperatures tend to destroy the circuitry this heat must be removed. Different types of cooling from ceramic chip packages to extra fans exist to tackle this problem. But cooling has two drawbacks: it is expensive (ceramic packages can be up to halve the chip costs) and in certain surroundings inacceptable (handys with fans?!). To summarize: power estimation and low power design are important for the production of reliable and inexpensive systems. When we look at the future this statement will be even more true as high-performance systems will become increasingly power-hungry. The figure below demonstrates this fact by showing the power dissipation development of state-of-the-art processors.  3. Basics 3.1. Types of power dissipation In the context of this page we restrict ourselves to synchronous CMOS circuits. In contrast to other design styles CMOS circuits have the property, that no direct circuit path exists between supply and ground when no activity exists within the circuit. Therefore static power consumption does only consist of leakage currents. These are considered of little importance for most of current designs. Lowering voltages will however drastically increase this type of current. The dynamic power consumption (related to internal switching) consist of two parts: 1. short circuit current. This current is due to the fact that a direct path from supply to ground exists for a short moment during the switching of a gate. This current is related to the duration of the switching process. 2. the capacitive load current. It stems from the loading and unloading of the inherent capacitancies of the circuit structures. These can be devided into three parts: a) output of the switching gate b) wiring attached to the output c) inputs of gates attached to the wiring 3.2. Fundamental equation Neglecting leakage currents we can express the power consumption directly as a function of the occuring switching activity (for short circuit current we could): P = a * C * Vdd2 * f where: P: power a: switching activity (expected number of 0->1 transitions per cycle) C: load capacitance Vdd: operation voltage f: Frequency This fundamental equation shows where energy can be saved: 1. Voltage Since the voltage has a quadratical impact on the power consumption, voltage reduction is a powerful way to minimize power consumption. Lowering the voltage however does have some drawbacks: a) performance decrease b) loss of compatibility to external voltage standards c) leakage increase (low voltage) d) feasability problem (very low voltage) 2. Physical capacitance As was mentioned above, the capacitances stems from interconnect and the inputs/outputs of gates. The gate capacitancies were the dominating part in the past. They are however reduced by the usage of smaller circuit technologies. That is why today interconnect is more critical. From the designers point of view physical capacitance can be reduced by minimizing the number of gates and the length and number of interconnect wires. Not that these goals are often conflicting against each other as well as the reduction of factors 1, 3 and 4. 3. Activity There is a multitude of design techniques to reduce activity. E.g. deactivation of unused circuitry, data encoding, architecture optimisation, etc. The goal is to perform the intended functionality with as few switches as possible. The reduction of switching activity can have a different impact on different parts of the circuit, however, depending on the capacitance switched. We therefore have to consider 'C' as well as 'a' in the above formula. In other words we look for: min sum(Csw_i) subject to speed, size and testibility constraints where: Csw_i = ai * Ci 'switched capacitance of gate/block i' This gives a minimal power consumption provided the frequency and supply voltage are fixed. One important phemomenon has to be mentioned here: the switches occuring in a circuit do most often not exactly match the switches that can be deduced from a functional description of the circuit. The reason for this is the existance of so called 'glichtes'. Glitches are spurios transitions of the circuit due to different arrival times of values at gate inputs. 4. Frequency The clock frequency is an important factor, since the destribution of the clock signal over the circuit can consume a lot of energy. This is true even if the switching activity within the circuit is very low. So what can be done? Make the clock as slow as possible while still staying within performance constraints. Think about introducing additional clocks. Some elaborate schemes use adaptive clock frequencies. Clock gating has become a very popular method recently: the clock signal is completely cut off for parts of the circuit which are temporarely unused. |
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