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Low Power Design Guide
Appendix
A Glossary
| Binding [ 12 ]: | | A binding is the explicit definition of a mapping between an algorithm's operations and resources e.g. adders, multipliers, memory, etc. A binding may imply that some resources are shared. Operands sharing a resource can not execute concurrently. |
| Clock Gating [ 1 ], [ 2 ]: | | A gated clock is a clock signal that can be stopped by a logic control signal which is computed during normal operation. When the gated clock is stopped, activity and therefore switching power consumption in the connected logic is reduced to zero. Notice that, differently from the supply shutdown case, power dissipation is not nullified. Leakage power is still dissipated. |
| Instrumentation: | | The process of adding additional functionality to a HDL specification to record activity on certain components, buses and signals. This functionality is needed only during simulation to make a subsequent power estimation possible. Throughout synthesis the original, non-instrumented code is used.
ORINOCO, a tool developed by OFFIS, automates instrumentation of behavioral VHDL descriptions. ToggleAnalysis, also developed by OFFIS, handles instrumentation of Verilog description at gate level. |
| IP: | | IP is the acronym for Intellectual Property. |
| Model: | | A model of a component/IP is created, if it's behavior is too complex or unknown during simulation/estimation. A parameterized functional model of a class of components/IPs will reduce simulation/estimation time by matters of magnitude. One will have to accept an appreciable error depending on the quality of the model.
The first step in building a model is the characterization. Secondly, model fitting must be executed. |
| Scheduling [ 12 ]: | | Whereas a control-dataflow graph, which can be developed from an algorithm, prescribes only dependencies among the operations, the scheduling of a control-dataflow graph determines the precise start time of each task. The start time must satisfy the original dependencies, which limit the amount of parallelism of the operations, because any pair of operations related by a sequence dependency may not execute concurrently. |
| SoC: | | System on a Chip. Instead of having a chipset of controllers, memories, bridges, codecs, etc. nowadays submicron technologies allow the cost-efficient integration of an entire system on one die. |
| Technology: | | Describes the chosen process which is offered by a vendor. |
B Register of Illustrations
figure 1: CMOS circuit 3
figure 2: Power Reduction Opportunities 5
figure 3: Alternative architectures that implement the same function: Effect of glitching 7
figure 4: Battery discharge lines 12
C Register of Equations
equation 1: 2
equation 2: 3
equation 3: 3
equation 4: 4
equation 5: 5
equation 6: 6
equation 7: 7
equation 8: 12
D Register of Literature
| [ 1 ] | | Gary K. Yeap, "Practical Low Power Digital VLSI Design", Kluwer Academic Publishers, 1998 |
| [ 2 ] | | Luca Benini & Giovanni De Micheli, "Dynamic Power Management, Design Techniques and CAD Tools", Kluwer Academic Publishers, 1998 |
| [ 3 ] | | Abdellatif Bellaouar & Mohamed I. Elmasry, "Low-Power Digital VLSI Design, Circuits and Systems", Kluwer Academic Publishers, 1995 |
| [ 4 ] | | Anand Raghunathan, Nirja K. Jha and Sujt Dey, "High-Level Power Analysis and Optimization", Kluwer Academic Publishers, 1998 |
| [ 5 ] | | H. J. Veendrick, "Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits", Journal of Solid-State Circuits, vol. SC-19, no. 4, pp. 468-473, August 1984 |
| [ 6 ] | | M. Farrahi, G. E. Tellez and M. Sarrafzadeh, "Memory segmentation to exploit sleep mode operation", Proceedings of the Design Automation Conference, pp. 36-41, June 1995 |
| [ 7 ] | | W. Nebel and J. Mermet, "Low Power Design in Deep Submicron Electronics", Kluwer Academic Publisher, 1997 |
| [ 8 ] | | A. Chandrakasan and R. Brodersen, "Low Power Digital CMOS design", Kluwer Academic Publisher, 1995 |
| [ 9 ] | | Frank Poppen, "Tools for Power Estimation", (unpublished internal paper), 2000 |
| [ 10 ] | | A. Gersho and R. Gray, "Vector Quantization and Signal Compression", Kluwer Academic Publishers, 1992 |
| [ 11 ] | | M. Stan and W. Burleson, "Limited-weight Codes for Low-power I/O", 1994 International Workshop on Low-power Design, pp. 209-214, April 1994 |
| [ 12 ] | | Giovanni De Micheli, "Synthesis and Optimization of Digital Circuits", McGraw-Hill Series in Electrical and Computer Engineering, 1994 |
| [ 13 ] | | J. Monteiro, S. Devadas, P. Ashar and A. Mauskar, "Scheduling Techniques to Enable Power Management", DAC-33:ACM/IEEE Design Automation Conference, pp. 349-352, 1996 |
| [ 14 ] | | Anand Raghunathan, Sujit Dey, Arkady Horak, Trevor Mudge and Kaushik Roy, "Low-Power System Design: Applications, Architectures and Design Methodologies", 37th Design Atomation Conference, |
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