CHARTER Low Power Design Guide
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Low Power Design Guide
2 Sources of Power Consumption When designers recognized power consumption as a design constraint, simple models were created. Power per MHz is still a commonly used representation of a component. With a closer look at power dissipation, it becomes obvious that the subject is not that simple. Electric current is not constant during operation; peak power is an important concern. The device will malfunction due to electro-migration and voltage drops even if the average power consumption is low. This chapter gives an overview of the sources of power consumption. A formula for average power is given in equation 1. equation 1: Pavg = Pdynamic + Pshort + Pleakage + Pstatic The four components are dynamic, short-circuit, leakage and static power consumption. The share of each part depends on the application and technology. In several cases e.g. Pleakage might be negligible, in others not. Have a look at 2.1 to 2.4 for a detailed explanation. 2.1. Capacitive Switching Activity Switching activity is a measure for the number of gates and their outputs that change their bit-value during a clock cycle. To toggle between logic zero and logic one capacities have to be discharged and charged. The electric current id that flows during this process causes a power dissipation Pdynamic. The current is dependent on the capacitive output load Cout and the supply voltage Vdd. In equation 2 this behavior is reproduced. equation 2: Pdynamic = KCoutVdd2 * f K is the average number of rising transitions during one clock cycle and f the clock frequency. It is interesting to see, that the supply voltage has a quadratic effect on dynamic power consumption. Reducing power supply will therefore have the greatest effect on saving power, taking into account that typically Pdynamic is responsible for 80% of Pavg. Unfortunately, designers don't have the freedom to choose the parameters arbitrarily. The chosen technology and the given timing constraints1 set a minimum and maximum range for the acceptable values. Until now, we assumed that all charge drawn from the power supply is collected by the output capacitances. Some current flows directly from power to ground and surmises a short-circuit current during bit switching. 2.2. Short-Circuit Currents CMOS circuits consist of a pull-up and pull-down network (see figure 1), which have a finite input fall/rise time larger then zero. During this short time interval, when the pull-down and pull-up network are conducting both, a current icc flows from power to ground. This current is called short-circuit current.  figure 1: CMOS circuit equation 3: Pshort = K(b / 12)(Vdd - 2VT)3 * f * t The resulting power consumption is calculated by equation 3. The origin of the formula is carried out in [ 5 ]. b is the gain factor of a MOS transistor, VT its threshold voltage and t is the rise/fall time of the gate inputs. Note that several authors observed that short-circuit power dissipation is usually a small fraction of total power usage, around 10%. Dynamic and short-circuit power depend on switching activity represented in the parameter K. As an effect, no power should be lost during idleness of a CMOS circuit, when K is zero. The existence of leakage currents shows another piece of reality. 2.3. Leakage Currents In [ 8 ] equation 4 is derived, which shows the structure of leakage power. equation 4: Pleakage = (Idiode + Isubthreshold) Vdd Idiode refers to the currents flowing through the reverse biased diodes that are formed between the diffusion regions and the substrate. Isubthreshold refers to currents flowing through transistors that are non-conducting. 2.4. Static Power Static power dissipation depends on a current flow from power to ground during idle time unlike short-circuit power dissipation, which occurs only during switching activity. NMOS circuits show high static power consumptions because power is connected directly to ground when a gate's output denounces logic zero, resolving into a great short circuit current. In well designed and flawless CMOS designs static power should be zero. If not, the reason could be e.g. a bus conflict where multiple drivers attempt to drive a signal to different logic values. 1 Reducing Vdd slows down charging of capacitances.
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